1. Field of the Invention
The present invention relates to methods for fabricating semiconductor integrated circuits, and more particularly to the fabrication of CMOS and bipolar circuit devices having local interconnect at the device level.
2. Description of the Prior Art
U.S. Pat. No. 4,948,755, issued Aug. 14, 1990 to Mo, entitled METHOD OF MANUFACTURING SELF-ALIGNED CONFORMAL METALLIZATION OF SEMICONDUCTOR WAFER BY SELECTIVE METAL DEPOSITION, discloses a method for fabricating a semiconductor integrated circuit which includes the selective deposition of metal, such as tungsten, into a contact opening formed in a dielectric layer, followed by the deposition of a thin silicon layer over the dielectric and metal-filled opening and the deposition of a second dielectric layer over the thin silicon layer. An opening or trench is formed in the upper second dielectric layer using the silicon as an etch stop, and a metal such as tungsten is selectively deposited to fill the trench wherever the exposed silicon is present. In one embodiment of the invention, prior to the filling of the trench, the exposed silicon is reacted with a blanket layer of a metal to form a metal silicide layer at the lower surface of the trench.
The process described in this patent uses selective deposition of tungsten into a via hole, and deposits a poly-Si etch stop after the contact stud is patterned and planarized. Thus, a metal layer is used as a plug and restricted in terms of wireability. Since the poly-Si is deposited after the metal is already patterned and then silicided in the via opening only, a poly-Si runner is left across the device in regions outside the vias. Although currents normally shunt through the least resistive path, the poly-Si electrically connects the metal plugs and may adversely affect electrical behavior. This may occur through added interlevel capacitance, degraded RC delay along the conductor, and the origin of potential differences between the via paths which may accelerate metal failures. Also, this method precludes the use of local interconnect in a CMOS device, where a strap from diffusion to gate is desired for maximum wireability.
Also, the structure described in U.S. Pat. No. 4,948,755 precludes dropping a contact from second metal to the contact metal (local interconnect at device level) because poly-Si is left across the wafer outside the vias and furthermore, a nonuniform silicide will result in the via hole because the via opening is pulled back outside the metal landing. When metal is deposited for silicidation of the etch stop, silicide will grow above both metal and oxide. This will result in a nonuniform silicide structure (viz., grain growth) which may increase contact resistance.
In the disclosed process, the poly-Si is patterned directly with the W conductor and it remains along the length of the W stripe so that no additional capacitance is created outside the interconnect pattern with the process. This is important because the W is not only used as a landing pad for studs, but also as a strap between various contact regions (diffusion to gate in CMOS). Also, the structure minimizes both the nonuniformities associated with silicidation and lateral growth effects above SiO2 since the structure does not have dissimilar materials in the via.
U.S. Pat. No. 4,764,484, issued Aug. 16, 1988 to Mo, entitled METHOD FOR FABRICATING SELF-ALIGNED, CONFORMAL METALLIZATION OF SEMICONDUCTOR WAFER, discloses a method for fabricating a VLSI multilevel metallization integrated circuit in which a first dielectric layer, a thin silicon layer, and then a second dielectric layer are deposited on the upper surface of a substrate. A trench is formed in the upper, second dielectric layer leaving a thin layer of the second dielectric layer overlying the thin silicon layer. A contact hole is then etched through the central part of the thin layer of the second dielectric layer, the thin silicon layer and the first dielectric layer to the surface of the substrate. Using the remaining outer portion of the thin layer of the dielectric layer as a mask over the underlying portion of the thin silicon layer, metal such as tungsten is selectively deposited into the contact hole. The remaining portion of the thin layer of the second dielectric layer is then removed and the trench is selectively filled with a metal that is in electrical contact with the metal filling the contact hole.
In U.S. Pat. No. 4,764,484, the poly-Si etch stop is not deposited until after deposition and planarization of the first metal, and is then removed before selective metal deposition. This leaves a poly-Si conductor between all via paths above the device.
U.S. Pat. No. 4,671,970, issued Jun. 9, 1987 to Keiser et al entitled TRENCH FILLING AND PLANARIZATION PROCESS, describes a process for forming planar trench oxide isolated integrated circuit devices. In particular, the process fills trenches of diverse widths, yet provides a final structure in which the narrow trench dielectrics, the wide trench dielectrics, and the active region surfaces are substantially coplanar. Furthermore, the process reduces the likelihood of creating voids in the narrow trenches. According to one practice, following the formation of the trenches in the substrate, successive layers of conformal silicon nitride, conformal polysilicon, and relatively conformal CVD oxide are formed to the relative depth of the trenches. A photoresist mask is then first selectively formed over the central regions of the wide trenches and used as a mask during the anisotropic etch of exposed oxide. The underlying polysilicon layer serves as an oxide etchant stop, and also provides the material from which the next successive oxidation partially fills the previously etched regions with thermal silicon dioxide. A further planarizing layer of oxide is then formed by poly deposition and oxidation. The nitride layer underlying the polysilicon layer prevents oxidation of the substrate. Fabrication is concluded with a planarization to the level of the active regions, including an etch of the nitride layer over such active regions.
In U.S. Pat. No. 4,671,970, a poly-Si etch stop with nitride underneath is converted to a dielectric (non-conductor) with oxidation. This layer is utilized for isolation in trench technology and does not carry current.
Japanese patent abstract JP63-168034, published Jul. 12, 1988 and entitled FORMATION OF MULTILAYER GATE ELECTRODE OF SEMICONDUCTOR DEVICE, describes a structure to reduce the leakage current while improving the reliability by a method wherein an insulating film is laid between the sidewalls of a first layer electrode of a semiconductor device to form the second layer electrode of the flattened surface.
The first layer electrode includes a polysilicon film provided with conductivity by phosphorus diffusion and an oxide film which are patterned and formed on another oxide film on a semiconductor substrate formed by thermal oxidation. Next, a polysilicon layer to be an etch-stopper film is laminated on the surface of this electrode and then a CVD oxide film is deposited and then etched back until the layer is exposed to flatten the surface. Finally, a polysilicon layer as the second electrode is formed on the surface to notably reduce the leakage current between sidewalls by excellent thick insulating film between the pattern sidewalls as well as the second electrode is formed stably on the flat surface to improve the reliability.
In JP-63-168034, an etchback planarization scheme is described wherein CVD oxide is etched back to expose poly-Si. This method is used to shape topography and minimize leakage at sidewalls by reducing severe steps.